This tutorial video explains how to create a Vivado project to implement ADX4 IP on a Kintex Ultrascale FPGA starting from a VHDL design example and using EV12AQ600-ADX-EVM demo board. This tutorial also delivers all steps to load the FPGA bitstream, retrieve sample data processed by the ADX4 IP using Vivado and analyze SFDR performance using a python Graphical User Interface (GUI).
0:00 Introduction - ADX4 principle
0:23 ADX4 IP cost, license key and design example
1:12 Demonstration
5:46 Conclusion