Learn how to simulate the EV12AQ600 ADC ESIstream serial interface using Vivado simulator and testbench available in each ESIstream package (KU FPGA, Versal ACAP…).
Learn about synchronization aspects and what the overall latency is made of.

EV12AQ600 ADC product webpage : https://semiconductors.teledyneimaging.com/en/products/data-converters/ev12aq600/

ESIstream web site: www.esistream.com

Youtube video: Get started with the ESIstream serial interface of the EV12AQ600 ADC and a Xilinx FPGA: https://youtu.be/Tb7OeSuZuQA

Youtube video: Start an ESIstream serial interface development with Versal ACAP and ADC EV12AQ600: https://youtu.be/hfHFWTn42pU

VHDL design example user guide : https://www.google.com/url?q=https%3A%2F%2Fgithub.com%2FESIstream%2FESIstream_documents%2Fraw%2Fmast...

White paper: Ease Design For Deterministic Latency In UltraFast Digitizing Systems : https://semiconductors.teledyneimaging.com/en/newsroom/ease-design-for-deterministic-latency-in-ultr...