You will learn how to easily download and create a Vivado project to implement the serial interface of the ADC EV12AQ600 or AQ605 to gain precious time in your development.
You will learn how to receive samples using a python script, Vivado hardware manager and Vivado Integrated Logic Analyzer (ILA).
You will learn how to test that the integration of the ESIstream serial interface is working properly.
0:00 Introduction
0:35 Contents
2:27 Download the VHDL design example
3:17 Create Vivado project
4:41 Load FPGA bitstream
6:04 Graphical User Interface