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Most Advanced Microwave Capable ADC: A Demonstration of EV10AS940

You will see Teledyne e2v latest ADC, EV10AS940 : 10-bit single channel, 12.8 GSps, outputs on a FMC evaluation board. The ADC is presented in this video on it’s FMC board to show the…

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Design an Agile Space Receiver Using EV12AQ600 ADC and PolarFire FPGA

Learn how to download and create a Libero project to gain precious time in development of your space receiver design using ADC EV12AQ600 and FPGA PolarFire. EV12AQ600 ADC qualification report:…

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State of the Art Microwave Capable ADC: a Demonstration of EV10AS940 FMC Board

You will see Teledyne e2v latest ADC, EV10AS940 : 10-bit single channel, 12.8 GSps, outputs on a FMC evaluation board. The ADC is presented in this video on it’s FMC board to show the…

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ADC Performance in Multiple Frequency Bands up to Ka with Only 195mW/GSPS and Single Ended Inputs.

The first live demonstration of the most advanced Analog-to-Digital Converter (ADC) from Teledyne e2v Semiconductors, EV10AS940. The latest 10-bit single channel 12.8 GSps ADC, with a max total power…

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Demonstration of Microwave ADC and DAC Digital Optical Harness PoC for Remote Architecture

DAC and ADC product webpage: https://semiconductors.teledyneimaging.com/en/products/data-converters/ White paper: Can deterministic digital phased array control be delivered over fiber? …

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Learn About ADX4 IP to Improve ADC RF Performance at Any Input Frequency and Temperature

This tutorial video explains how to create a Vivado project to implement ADX4 IP on a Kintex Ultrascale FPGA starting from a VHDL design example and using EV12AQ600-ADX-EVM demo board. This tutorial…

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Simulate EV12AQ600 ADC ESIstream Serial Interface

Learn how to simulate the EV12AQ600 ADC ESIstream serial interface using Vivado simulator and testbench available in each ESIstream package (KU FPGA, Versal ACAP…). Learn about…

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Start an ESIstream Serial Interface Development with Versal ACAP and ADC EV12AQ600

Get all information to accelerate your ESIstream high-speed serial interface development introducing the Versal ACAP ESIstream package based on the VCK190 Versal AI core development kit. The Versal…

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Get Started with the ESIstream Serial Interface of the EV12AQ600 ADC and a Xilinx FPGA

You will learn how to easily download and create a Vivado project to implement the serial interface of the ADC EV12AQ600 or AQ605 to gain precious time in your development. You will learn how to…

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Learn Time-interleaved EV12AQ600 ADC Mismatch Error Correction with Kintex Ultrascale FPGA ADX IPs

A brief introduction to the ADX4 and ADX2 IPs for the EV12AQ600 or 605 ADC. ADX IP allows you to cancel time interleaving mismatches effects like gain, phase and DC-offset by real time post…

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Learn about multi-ADC synchronization in only 7 minutes!

This exclusive tutorial video will give you a useful overview of a multi-ADC synchronization technique, from the needs of synchronous and deterministic behavior within a multi-channel system to a…

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Synchronisation for ADCs used in Phased Arrays

Multi-element phased array radar systems are being developed with greater number of channels to achieve more flexibility, speed and precision. The ability to digitize each channel brings the…

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Ka band Direct Conversion ADCs and DACs

Direct conversion system advantages include increased flexibility, reduced complexity, weight and power consumption. Direct conversion to and from Ka-band frequencies is now possible with good…

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Ka-band Direct Digital Conversion is Now Within Reach of Modern Data Converters

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TUTORIAL - ESI Stream IP, Ease your way to Deterministic Data Serialization

This video is about data transfer and removing a critical speed limitation in data conversion systems. It is a discussion about adopting either a ready-made standard or considering the alternative;…

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Get going with ESIstream projects! - Tutorial

This webinar session introduces serial data transfer in data conversion systems. It presents implementation choices to consider at the beginning of a project when using ESIstream including how to…

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